Semiconductor memory blocks can be well defined and separated out from a system much more easily than can other components of other semiconductors. Because of the stand-alone nature of memory blocks, many semiconductor memory developers outsource designing memory modules. The modular nature of memory blocks and the demand for embedded memories, as well as the fact that the memory core may utilize new technologies in which the system design team lacks design expertise, have all resulted in the growth of use of memory compilers.
The first published static random access memory (SRAM) compiler, known as RAMGEN, was developed at Texas Instruments® in 1986 and was strictly a layout generator. This tool simply connected previously designed leaf cells into a parameterized static random access memory (“SRAM”) configuration that could be fabricated with either a 2.0 or 3.0 μm complementary metal-on-silicone (CMOS) process. Since that time, numerous SRAM compilers have been developed.
Designing for the lowest power requires small cells. Adding peripheral circuits such as self-timed clocking, clock-partitioning, reduced bit-line swing, and array banking circuits may aid in delivery of the lowest possible power. End of cycle shut-off logic and the addition of a memory disable pin may also ensure zero quiescent current regardless of the state of the clock or input pins facilitating very low power consumption when the memory is idle.
As used with memory compilers, a leaf cell is typically defined as a cell that contains a transistor or transistor cell. Except for the memory cell, all leaf cells are typically laid out once the design is complete. Power and feedthroughs are typically included in the leaf cell.